AZC199-04C low capacitance high esd level protection array for high speed i/o port features description ? esd protect for 4 high-speed i/o lines and one vdd line AZC199-04C is a design which includes esd rated diode arrays to protect high speed data interfaces. the AZC199-04C has been specifically designed to protect sensitive components which are connected to data and transmission lines from over-voltage caused by electrostatic discharging (esd). ? provide esd protection for each line to iec 61000-4-2 (esd) 15kv (air/contact) iec 61000-4-4 (eft) 50a (5/50ns) iec 61000-4-5 (lightning) 5a (8/20 s) ? for low operating voltage applications: 5v, 4.2v, 3.3v, 2.5v etc. ? low capacitance : 1.0pf typical AZC199-04C is a uniq ue design which includes esd rated, low capacitance steering diodes and a unique design of clamping cell which is an equivalent tvs diode in a single package. during transient conditions, the steering diodes direct the transient to either the power supply line or to ground line. the internal unique design of clamping cell prevents over-voltage on the power line, protecting any downstream components. besides, there is a back-drive protection design in AZC199-04C for power-down mode operation. ? fast turn-on and low clamping voltage ? array of esd rated diodes with internal equivalent tvs diode ? solid-state silicon-avalanche and active circuit triggering technology ? back-drive protection for power-down mode ? small sot363 package saves board space ? green part applications ? video graphics cards AZC199-04C ma y be used to meet the esd immunity requirements of iec 61000-4-2, level 4 (? 15kv air, ? 8kv contact discharge). ? digital visual interface (dvi) ? usb2.0 power and data lines protection ? notebook and pc computers ? monitors and flat panel displays circuit diagram 1 3 4 6 5 2 pin configuration 6 5 4 1 2 3 i/o 1 i/o 2 i/o 3 i/o 4 vdd gnd sc70-6l (top view) (sot-363) revision 2010/02/10 ?2010 amazing micro. 1 www.amazingic.com www.datasheet.co.kr datasheet pdf - http://www..net/
AZC199-04C low capacitance high esd level protection array for high speed i/o port revision 2010/02/10 ?2010 amazing micro. 2 www.amazingic.com specifications absolute maximum ratings parameter parameter rating units peak pulse current (tp =8/20 ? s) (i/o pins) i pp 5 a operating supply voltage (vdd-gnd) v dc 6 v esd per iec 61000-4-2 (air/contact) v esd 15 kv lead soldering temperature t sol 260 (10 sec.) o c operating temperature t op -55 to +85 o c storage temperature t sto -55 to +150 o c dc voltage at any i/o pin v io (gnd ? 0.5) to (vdd + 0.5) v electrical characteristics parameter symbol conditions min typ max units reverse stand-off voltage v rwm pin 5 to pin 2, t=25 o c 5 v reverse leakage current i leak v rwm = 5v, t=25 o c, pin 5 to pin 2 5 ? a channel leakage current i ch-leak v pin5 = 5v, v pin2 = 0v, t=25 o c 1 ? a reverse breakdown voltage v bv i bv = 1ma, t=25 o c, pin 5 to pin 2 6 9 v forward voltage v f i f = 15ma, t=25 o c, pin 2 to pin 5 0.85 1 v esd clamping voltage ?i/o v clamp_io iec 61000-4-2 +6kv, t=25 o c, contact mode, any channel pin to ground 11 v esd clamping voltage ?vdd v clamp_vdd iec 61000-4-2 +6kv, t=25 o c, contact mode, vdd pin to ground 9.5 v esd dynamic turn on resistance ?i/o r dynamic_io iec 61000-4-2 0~+6kv,t=25 o c, contact mode, any channel pin to ground 0.3 ?? esd dynamic turn on resistance ?vdd r dynamic_vdd iec 61000-4-2 0~+6kv, t=25 o c, contact mode, vdd pin to ground 0.15 ?? lightning clamping voltage v lightning_io i pp =5a, tp=8/20? s, t=25 o c any channel pin to ground 8.5 v lightning clamping voltage v lightning_vdd i pp =5a, tp=8/20? s, t=25 o c vdd pin to ground 7.7 v channel input capacitance -1 c in-1 v pin5 =5v, v pin2 =0v, v in =2.5v , f =1mhz, t=25 o c, any channel pin to ground 1.0 1.2 pf channel input capacitance - 2 c in-2 v pin5 =floated,v pin2 =0v, v in =2.5v ,f=1mhz, t=25 o c,any channel pin to ground 1.5 1.8 pf channel to channel input capacitance -1 c cross-1 v pin5 =5v, v pin2 =0v, v in =2.5v , f =1mhz, t=25 o c , between channel pins 0.15 0.2 pf channel to channel input capacitance -2 c cross-2 v pin5 =floated ,v pin2 =0v, v in =2.5v ,f =1mhz,t=25 o c,between channel pins 0.18 0.23 pf variation of channel input capacitance -1 c in-1 v pin5 =5v , v pin2 =0v, v in =2.5v , f =1mhz, t=25 o c , channel_x pin to ground - channel_y pin to ground 0.08 0.1 pf variation of channel input capacitance -2 c in-2 v pin5 =floated , v pin2 =0v, v in =2.5v , f =1mhz, t=25 o c , channel_x pin to ground - channel_y pin to ground 0.06 0.08 pf www.datasheet.co.kr datasheet pdf - http://www..net/
AZC199-04C low capacitance high esd level protection array for high speed i/o port typical characteristics input voltage (v) 0.00.51.01.52.02.53.03.54.04.55.0 input capacitance (pf) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 typical variation of c in vs. v in f = 1mhz, t=25 o c, vdd=5v vdd=floated peak pulse current (a) 4.55.05.56.06.57.07. 5 clamping voltage (v) 0 1 2 3 4 5 6 7 8 9 10 11 12 clamping voltage vs. peak pulse current waveform parameters: tr=8 ? s td=20 ? s i/o pin to gnd pin peak pulse current (a) 5 6 7 8 9 10 11 forward clamping voltage (v) 0 1 2 3 4 5 forward clamping voltage vs. peak pulse current waveform parameters: tr=8 ? s td=20 ? s i/o pin to gnd pin vdd p in to gnd pin v dd pin to gnd pin transmission line pulsing (tlp) measurement transmission line pulsing (tlp) voltage (v) 024681012 transmission line pulsing (tlp) current (a) 0 2 4 6 8 10 12 14 16 18 v_pulse 100ns pulse from a transmission line dut tlp_i + - tlp_v i/o to gnd transmission line puls ing (tlp) measurement transmission line puls ing (tlp) voltage (v) 02468 10 transmission line pulsing (tlp) current (a) 0 2 4 6 8 10 12 14 16 18 v_pulse 100ns pulse from a transmission line dut tlp_i + - tlp_v vddto gnd revision 2010/02/10 ?2010 amazing micro. 3 www.amazingic.com www.datasheet.co.kr datasheet pdf - http://www..net/
AZC199-04C low capacitance high esd level protection array for high speed i/o port applications information a. design considerations the esd protection scheme for system i/o connector is shown in the fig. 1. in fig. 1, the diodes d1 and d2 are general used to protect data line from esd stress pulse. the diode d3 is a back-drive protection design, which blocks the dc back-drive current when the potential of i/o pin is greater than that of vdd pin. if the power-rail esd clamping circuit is not placed between vdd and gnd rails, the positive pulse esd current (i esd1 ) will pass through the esd current path1. thus, the esd clamping voltage v cl of data line can be described as follow: revision 2010/02/10 ?2010 amazing micro. 4 www.amazingic.com v cl = fwd voltage drop of d1 + breakdown voltage drop of d3 + supply voltage of vdd rail + l 1 ? d(i esd1 )/dt + l 2 ? d(i esd1 )/dt where l 1 is the parasitic inductance of data line, and l 2 is the parasitic inductance of vdd rail. an esd current pulse can rise from zero to its peak value in a very short time. as an example, a level 4 contact discharge per the iec61000-4-2 standard results in a current pulse that rises from zero to 30a in 1ns. here d(i esd1 )/dt can be approximated by i esd1 / t, or 30/(1x10 -9 ). so just 10nh of total parasitic inductance (l 1 and l 2 combined) will lead to over 300v increment in v cl ! besides, the esd pulse current which is directed into the vdd rail may potentially damage any components that are attached to that rail. moreover, it is common for the forward voltage drop of discrete diodes to exceed the damage threshold of the protected ic. this is due to the relatively small junction area of typical discrete components. of course, the discrete diode is also possible to be destroyed due to its power dissipation capability is exceeded. the AZC199-04C has an integrated power-rail esd clamped circuit between vdd and gnd rails. it can successfully overcome previous disadvantages. during an esd event, the positive esd pulse current (i esd2 ) will be directed through the integrated power-rail esd clamped circuit to gnd rail (esd current path2). the clamping voltage v cl on the data line is small and protected ic will not be damaged because power-rail esd clamped circuit offer a low impedance path to discharge esd pulse current. fig. 1 application of positive esd pulse between data line and gnd rail. www.datasheet.co.kr datasheet pdf - http://www..net/
AZC199-04C low capacitance high esd level protection array for high speed i/o port b. device connection AZC199-04C can provide protectio n for 4 i/o signal lines simultaneously. if the number of i/o signal lines is less than 4, the unused i/o pins can be simply left as nc pins. the AZC199-04C is designed to protect four data lines and power rails from transient over-voltage (such as esd stress pulse). the device connection of AZC199-04C is shown in the fig. 2. in fig. 2, the four protected data lines are connected to the esd protection pins (pin1, pin3, pin4, and pin6) of AZC199-04C. the ground pin (pin2) of AZC199-04C is a negative reference pin. this pin should be directly connected to the gnd rail of pcb (printed circuit board). to get minimum parasitic inductance, the path length should keep as short as possible. in addition, the power pin (pin 5) of AZC199-04C is a positive reference pin. this pin should directly connect to the vdd rail of pcb., then the vdd rail also can be protected by the power-rail esd clamped circuit (not shown) of AZC199-04C. in some cases, systems are not allowed to be reset or restart after the esd stress directly applying at the i/o-port connector. under this situation, in order to enhance the sustainable esd level, a 0.1 ? f chip capacitor can be added between the vdd and gnd rails. the place of this chip capacitor should be as close as possible to the AZC199-04C. in some cases, there isn?t power rail presented on the pcb. under this situation, the power pin (pin 5) of AZC199-04C can be left as floating. the protection will not be affected, only the load capacitance of i/o pins will be slightly increased. fig. 3 shows the detail connection. 1 2 34 5 6 AZC199-04C to protected ic to protected ic i/o 1 i/o 2 i/o 3 i/o 4 to i/o-port connector to i/o-port connector i/o 4 i/o 3 i/o 2 i/o 1 gnd rail data line data line data line data line vdd rail *optional 0.1 ? f chip cap. fig. 2 data lines and power rails connection of AZC199-04C. 1 2 34 5 6 vdd floated AZC199-04C to protected ic to protected ic i/o 1 i/o 2 i/o 3 i/o 4 to i/o-port connector to i/o-port connector i/o 4 i/o 3 i/o 2 i/o 1 data line data line data line data line gnd rail fig. 3 data lines and power rails connection of AZC199-04C. vdd pin is left as floating when no power rail presented on the pcb. revision 2010/02/10 ?2010 amazing micro. 5 www.amazingic.com www.datasheet.co.kr datasheet pdf - http://www..net/
AZC199-04C low capacitance high esd level protection array for high speed i/o port c. application AZC199-04C is designed for protecting high speed i/o ports from very high over-voltage caused by electrostatic discharging (esd). thus, a lot of kinds of high speed i/o ports can be the applications of AZC199-04C, especially, the vga and dvi ports with the esd spec. of contact-15kv, class-c above. the vga output port revision 2010/02/10 ?2010 amazing micro. 6 www.amazingic.com fig. 4 show s the schematic of esd protection design for a vga output port on a host system, (e.g. the source, such as mb, nb, media player?), where two AZC199-04C are used. the AZC199-04C has been integrated with back-drive protection diode for preventing the back-drive current to occur. thus, no extra bav70 for preventing the back-drive current to occur is needed. the back-drive current occurs as shown in fig, 5. when the source stays at off state, at the source connector, the vga5v pin was wished to be at zero potential. at this moment, if without the integrated back-drive current protection diode, the display device stays at on state, and the pulled high signals will produce a current back drive to the source?s vga5v power plate as shown in fig. 5. this back drive current may make vga5v be not at zero potential, which may lead system to an abnormal state. therefore, it should be eliminated, and the integrated back-drive protection diode can eliminate this current. the vga input port in contrast with the design for a vga output port, the schematic of esd protection design for a vga input port on a display system is shown in fig. 6. in most of vga input circuit designs, there are always two power supplies, one is from the connector?s dsub-5v pin which potential comes from another vga output port, the other is from the own power supply circuit of the vga input port, system 5v. the vdd pin of AZC199-04C is directly connected to the connector?s dsub-5v pin to block the esd event which comes from the dsub-5v pin. vga5v ddca_sda vsync hsync ddca_scl vga5v green red detect blue red green blue ddca_scl ddca_sda vsync hsync dig_gnd red_gnd green_gnd blue_gnd vga5v gnd 15-pin vga connector detect video filter 75 ? red video filter 75 ? green video filter 75 ? blue fb vsync fb hsync fb ddc_data fb ddc_clk signals from scaler fb detect esd protection design AZC199-04C 6 5 4 1 2 3 AZC199-04C 6 5 4 1 2 3 system_5v vga5v fig. 4 the esd design for a vga output port which two AZC199-04C are used. www.datasheet.co.kr datasheet pdf - http://www..net/
AZC199-04C low capacitance high esd level protection array for high speed i/o port revision 2010/02/10 ?2010 amazing micro. 7 www.amazingic.com ddca_sda vdd 100 ? 10k ? to scaler ddc_data 6 5 4 1 2 3 vdd bav70 vga5v system 5v 0.1uf fb ddca_sda vga5v ddca_sda monitor site source site (e.g. mb) fig. 5 the occurred back drive current when the source is at off state and the display device is at on state. ddca_sda vsync hsync ddca_scl vsync hsync red green blue ddca_scl ddca_sda vsync hsync dig_gnd red_gnd green_gnd blue_gnd dsub-5v gnd fb 0 ? 75 ? red 75 ? green 75 ? blue fb 0 ? fb 0 ? 5.6pf 0.047uf 100 ? to scaler red 5.6pf 0.047uf 100 ? to scaler green 5.6pf 0.047uf 100 ? to scaler blue 2.2k ? 220pf 1k ? 2.2k ? 33pf 1k ? fb 120 ? ddca_sda system 5v 100 ? 10k ? ddca_scl 100 ? 10k ? to scaler vsync to scaler hsync to scaler ddc_data to scaler ddc_clk 15-pin vga connector dsub-5v green red detect blue AZC199-04C AZC199-04C detect esd protection design 6 5 4 1 2 3 dsub-5v 6 5 4 1 2 3 dsub_5v system 5v system 5v bav70 or bat54 eeprom fig. 6 the esd design for a vga input port which two AZC199-04C are used. www.datasheet.co.kr datasheet pdf - http://www..net/
AZC199-04C low capacitance high esd level protection array for high speed i/o port mechanical details sc70-6l (sot363) package diagrams p ackage dimensions t op view side view end view revision 2010/02/10 ?2010 amazing micro. 8 www.amazingic.com www.datasheet.co.kr datasheet pdf - http://www..net/
AZC199-04C low capacitance high esd level protection array for high speed i/o port land layout dimensions index millimeter inches a 0.40 0.016 b 0.85 0.033 c 0.65 0.026 d 1.85 0.073 e 1.00 0.039 f 2.70 0.106 notes: this land la yout is for reference purposes only. please consult your manufacturing partners to ensure your company?s pcb design guidelines are met. marking code part number marking code AZC199-04C (green part) c12xy s15x c15x c 12xy c12 = device code x = date code y = control code revision 2010/02/10 ?2010 amazing micro. 9 www.amazingic.com www.datasheet.co.kr datasheet pdf - http://www..net/
AZC199-04C low capacitance high esd level protection array for high speed i/o port revision 2010/02/10 ?2010 amazing micro. 10 www.amazingic.com revision history revision modification description revision 2010/02/10 formal release. www.datasheet.co.kr datasheet pdf - http://www..net/
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